As is well known to those skilled in the art of designing digital data signal receivers, it is common in such receivers to use a phase-locked loop (PLL) to synchronize the receiver's internal clock with the "carrier frequency" of the incoming signal. The clock signal generated by the PLL is herein called the "recovered clock". An essential function of a clock and data recovery circuit is the recovery of the clock signal from the incoming data transitions such that the recovered clock is able to sample the incoming data at the optimum positions (centers) of the data symbols.
In many data communication systems, data is transmitted using NRZ (non-return to zero) or NRZI (non-return to zero inverted) data coding, because such coding is efficient in bandwidth. In the NRZ coding scheme, a "1" bit is transmitted by a bit frame with a logic high voltage for the entire bit frame, and a "0" bit is transmitted by a bit frame with a logic low voltage for the entire bit frame. In the NRZI coding scheme, a "0" bit is transmitted by a bit frame in which there is no signal transition, and a "1" is transmitted by a bit frame in which there is a signal transition. In both the NRZ and NRZI coding schemes, data signals have no spectral component at the clock frequency. In both coding schemes, the data stream may have no signal transitions for several successive bit frames, which creates difficulties for many prior art phase detectors.
If several bit frames are overlaid on an oscilloscope screen, a pattern known as the "eye opening" is formed. Within each bit frame, the signal value must be sampled in order to decode the bit value for that frame. While sampling in the center of each bit frame is the ideal, circuit delays and other signal distortions may make it extremely difficult for the PLL to precisely track the bit frame center.
One prevalent problem found in many prior art phase detectors used in NRZ data recovery circuits is the "delay mismatch problem". As shown in FIG. 1, such prior art phase detectors (e.g., multiplier or exclusive-OR phase detectors) require that a non-linear element (such as a squaring device) be placed before the phase detector in order to reproduce the spectral component of the input data signal's clock frequency. A primary problem with this scheme is that data signals in the data recovery signal path must be delayed by the same amount of time as the signals which go through the non-linear element used for clock recovery. Any mismatch between these two distinct circuits (i.e., the non-linear device and a delay matching circuit) will cause mis-alignment of the recovered clock from the optimum sampling point, resulting in static alignment errors (SAE) and a higher chance of data decoding error.
As will be shown below, the present invention overcomes the delay mismatch problem by eliminating the need for separate signal paths for data recovery and clock recovery, as well as using identical circuits, with virtually identical delay, for both data and clock signals.
Another problem addressed by the present invention concerns "duty-cycle distortion". In very high speed optical data communications, such as Fiber Distribution Data Interface (FDDI) systems, the incoming data may contain large duty-cycle distortions (DCD), and data pattern dependent jitters (DDJ). DCD is characterized by positive going transitions and/or negative going transitions of the data signal being shifted from their ideal position within each bit frame. For a simple analogy, DDJ can be considered to generate similar effects as DCD, in that it dynamically changes the eye opening in which the signal can be sampled accurately.
In order to accurately decode the incoming data stream, and to maintain acceptable bit error rates even when the data stream contains duty cycle distortions or data pattern dependent jitters, it is preferable for the phase detector to provide "proportional phase error information" to the PLL so that the PLL can locate the statistical center of the eye opening.
For incoming NRZ or NRZI data streams with heavy duty-cycle distortions, there exist large differences between the phase-error information generated by positive and negative data transitions. As a result, conventional edge-triggered phase detectors require two phase detectors for phase error averaging: one for sensing positive transitions and one for sensing negative transitions. Delay mismatch between the clock recovery and data recovery signal paths is still a serious problem. Moreover edge-triggered phase detectors are intolerant to input signal glitches.
Another prior art phase detector, known as a "quantized phase sampler" circuit, samples an incoming NRZ data stream at two times the clock frequency and hunts for data transitions to provide phase error information. There is no delay mismatch problem because the recovered data is derived from the phase error sampling path. However, due to the edge-hunting nature of the circuit, there is no proportional phase-error information for the circuit to locate the center of the eye-opening when the incoming data stream contains severe DCD/DDJ distortions, causing the recovered clock to wander.
It is an object of the present invention to provide a phase detector that overcomes the problems with prior art phase detectors mentioned above.